After finish writing my SystemVerilog code and being able to compile them successfully in Quartus Prime, I decided to launch the simulation to verify whether my design was sound. However, during the simulation compilation phase, I encounter the following issue:
# vlog -reportprogress 300 -sv -work work "+incdir+/home/user/Desktop/project/src" /home/user/Desktop/project/src/component1.sv # ** Error: /home/user/Desktop/project/src/component1.sv(10): Cannot find `include file "header_if.svh" in directories: # /home/user/Desktop/project/src, /home/user/intelFPGA_lite/21.1/questa_fse/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /home/user/intelFPGA_lite/21.1/questa_fse/uvm-1.1d/../verilog_src/uvm-1.1d/src
The Questasim cannot find the header files I have in a different folder. After examining the base simulation tlc script
QUARTUS_INSTALL_PATH/quartus/common/tcl/internal/nativelink/modelsim.tcl, it looks like Quartus just put the source file's directory as the include folder and there does not seem to have an option to change this.
A solution to this is to add the header files into your testbench configuration in nativelink under
Assignment->Settings->EDA Tool Settings->Simulation. Click on the
Test Benches button and add the header files in one of your testbench settings. After this step, the simulation tool should be able to find the interface files and compile properly.
In the same setting window (
Assignment->Settings->EDA Tool Settings->Simulation), you can also specify the waveform script to be loaded for the simulation: